Recently, flat panel displays such as liquid crystal displays have been considered to be important items more and more for the progress of the enhanced video and information oriented society and for the wide spread of multimedia systems. Because those liquid crystal displays have such merits as low power consumption, thin and light structure, etc., they are employed widely as displays of portable terminal devices, etc.
A liquid crystal display has a liquid crystal panel for displaying images and a driving circuit for driving the liquid crystal panel. An active matrix type liquid crystal panel has an element substrate, a counter substrate, and liquid crystal held between those substrates. On the element substrate are formed horizontal scanning lines and vertical data lines respectively. And plural pixel electrodes are formed like a matrix between those scanning and data lines. An active element such as a TFT (Thin Film Transistor) is provided around each node of those scanning and data lines. Each TFT gate electrode is connected to a scanning line, each source electrode is connected to a data line, and each drain electrode is connected to a pixel electrode respectively.
Common electrodes facing a pixel electrode are formed on the counter substrate. One end of a liquid crystal capacity, which is a capacitive load, is connected to a pixel electrode. The other end of the liquid crystal capacity is connected to a common electrode facing a pixel electrode formed on the counter substrate. Consequently, the liquid crystal capacity is connected equivalently to a TFT drain electrode.
A scanning line driving circuit is connected to the scanning lines and a data line driving circuit is connected to the data lines respectively. The scanning line driving circuit scans the scanning lines sequentially from up to down to enable the data line driving circuit to apply a voltage to each pixel electrode through a TFT. The common electrode driving circuit applies a proper voltage to each common electrode. This is why the liquid crystal is applied a voltage equivalent to a potential difference between the pixel electrode and the common electrode. The liquid crystal display changes such a voltage applied to the liquid crystal to change the ordering of the liquid crystal and changes the light transmittance to make a gradation display.
In the case of a known liquid crystal display, the polarity of a voltage applied to each pixel electrode from a data line through a TFT (hereinafter, to be referred to as a pixel voltage) is inverted at every predetermined period. By inverting the polarity of such a voltage applied to the liquid crystal to make AC driving, the degradation of the characteristics of the liquid crystal to be caused by DC driving is suppressed. As an AC driving method, for example, there is a well known dot inversion driving method, which inverts the polarity of the pixel voltage with respect to each pixel.
Generally, an operational amplifier subjected to voltage follower connection is used as an output circuit used as a driving circuit employed for a liquid crystal display. The frequency characteristic of the operational amplifier changes according to a change of the driving load condition. If the load frequency characteristic changes in the operational amplifier employed for a driving circuit, the operational amplifier comes to oscillate, thereby causing a trouble in the display of the liquid crystal panel.
There are some known methods for improving the frequency characteristic of the operational amplifier and one of the methods is phase compensation (hereinafter, to be referred to as mirror compensation) realized with use of a mirror capacity (e.g., Laid open Japanese application No. 2005-124120 A). FIG. 9 shows a configuration of a conventional driving circuit 10 described in the JP 2005-124120 A. As shown in FIG. 9, the conventional driving circuit 100 has an N receiving differential amplifier 101, a P receiving differential amplifier 102, and an AB class amplifying circuit 103. The driving circuit of the liquid crystal display described in the JP 2005-124120 A uses the AB class amplifier 103 for making mirror compensation for enabling Rail-to-Rail inputs/outputs.
The AB class amplification circuit 13 has a P channel MOS transistor 104 connected between an output terminal and a power supply terminal and an N receiving channel output MOS transistor 105 connected between the output terminal and a ground terminal. The gate of the P channel MOS transistor 104 is connected to an output line of the N receiving differential amplifier 101. The gate of the N channel MOS transistor 105 is connected to an output line of the P receiving differential amplifier 105. In the AB class output circuit 103, a pair of mirror capacities 106 and 107 for phase compensation are connected between the gate of each of a pair of P channel MOS transistors 104 and an output terminal Vout and between the gate of each of a pair of N channel output MOS transistors 105 and the output terminal Vout respectively.
This pair of mirror capacities 106 and 107 is effective to improve the frequency characteristic of the differential type AB amplifier 1. In this case, the larger the mirror capacity, which is assumed to be a phase compensation capacity, is, the more the frequency characteristic is improved.
If a driving circuit including an operational amplifier for mirror compensation, which enables Rail-to-Rail inputs/outputs, is used for the AC driving that inverts the voltage polarity alternately just like the above described dot inversion driving method, the following cases will arise in each polarity inversion, thereby the through-current increases. As a result, the through-rate of the operational amplifier is lowered. This has been a conventional problem.
(1) When Polarity Output is Inverted from Positive to Negative
If the polarity of the polarity inverted signal is inverted from positive to negative, the gate voltage rises at each of the P channel MOS transistor 104 and the N channel MOS transistor 105. As a result, the ON resistance of the P channel MOS transistor 104 rises while the ON resistance of the N channel MOS transistor 105 falls, then the Vout falls. At the moment when the polarity of this Vout is inverted from positive to negative, the Vout makes a voltage fall suddenly, thereby the charge goes to the mirror capacity 106. Consequently, the gate voltage of the P channel MOS transistor 104 falls and its ON resistance is delayed to rise. Therefore, at such a polarity inversion from positive to negative, the ON resistance of both P channel MOS transistor 104 and N channel MOS transistor 105 is lowered at the same time in a period, in which a large through-current comes to flow.
(2) When Polarity Output is Inverted from Negative to Positive
If the polarity of the polarity inverted signal is inverted from negative to positive, the gate voltage falls at both the P channel MOS transistor 104 and the N channel MOS transistor 105. As a result, the ON resistance of the P channel MOS transistor 104 falls while the ON resistance of the N channel MOS transistor 105 rises, then the Vout rises. At the moment when the polarity of this Vout is inverted from negative to positive, the Vout makes a voltage rise suddenly, thereby the charge goes to the mirror capacity 106. Consequently, the gate voltage of the N channel MOS transistor 105 rises and its ON resistance is delayed to rise. Therefore, even at such a polarity inverted output from negative to positive, the ON resistance of both P channel MOS transistor 104 and N channel MOS transistor 105 is lowered at the same time in a period, in which a large through-current comes to flow.
If AC driving is adopted for a liquid crystal panel such way, the operational amplifier in the driving circuit keeps inverting the output voltage to drive the liquid crystal, which is a capacitive load. In that case, each time the output voltage polarity is inverted, the output voltage comes to amplitude significantly. And to obtain a desired output voltage when the output voltage polarity is inverted, the ON resistance of one of the transistors 104 and 105 is lowered and the ON resistance of the other transistor is raised. In the case of the conventional mirror compensation, the output of the operational amplifier comes to affect the gate of each output transistor due to the mirror capacity. Consequently, the mirror capacity causes a delay of the rising of the ON resistance of the transistor that is expected to increase the ON resistance to limit the output. As a result, the ON resistance of both transistors 104 and 105 falls at the same time in a period, thereby the through-current increases and the through rate of the operational amplifier is lowered. And such an increase of the through-current causes heat generation and EMI (Electro-Magnetic Interference) in chips.